Implementation of Multiple HBT Variants in 0.18 Micron Silicon Germanide BiCMOS Technology

Implementation of Multiple HBT Variants in 0.18 Micron Silicon Germanide BiCMOS Technology
Author: Rebecca Shun Ying Au
Publisher:
Total Pages: 178
Release: 2006
Genre:
ISBN: 9780494404270


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The SiGe BiCMOS technology is the cost-effective solution for high-speed communications applications due to its RF/analog properties and CMOS compatibility. The main challenge with the optimization of SiGe HBT is to achieve both high speed and high breakdown performance simultaneously. This thesis investigates the optimization of the collector profile to attain multiple variants of SiGe HBTs, namely high speed, standard and high voltage devices, in one BiCMOS technology. Using process and device simulations, the device performance is enhanced by base and collector profile optimization to minimize base transit time and collector delay. Variants of SiGe HBTs with multiple cutoff frequencies and breakdown voltages are achieved by proper choice of collector doping concentration using selectively-implanted collectors (SIC). Three SiGe npn transistors with fT/BVCEO values of 80GHz/2V, 60GHz/2.9V and 40GHz/4.8V are successfully fabricated in standard 0.18 mum CMOS technology by an industrial foundry, with minimal extra process complexity.


Implementation of Multiple HBT Variants in 0.18 Micron Silicon Germanide BiCMOS Technology
Language: en
Pages: 178
Authors: Rebecca Shun Ying Au
Categories:
Type: BOOK - Published: 2006 - Publisher:

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The SiGe BiCMOS technology is the cost-effective solution for high-speed communications applications due to its RF/analog properties and CMOS compatibility. The
Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond
Language: en
Pages: 115
Authors: Guilei Wang
Categories: Technology & Engineering
Type: BOOK - Published: 2019-09-20 - Publisher: Springer Nature

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This thesis presents the SiGe source and drain (S/D) technology in the context of advanced CMOS, and addresses both device processing and epitaxy modelling. As