Selected Papers on Resolution Enhancement Techniques in Optical Lithography

Selected Papers on Resolution Enhancement Techniques in Optical Lithography
Author: F. M. Schellenberg
Publisher: SPIE-International Society for Optical Engineering
Total Pages: 910
Release: 2004
Genre: Integrated circuits
ISBN:


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Optical lithography for integrated circuits is undergoing a renaissance with the adoption of Resolution Enhancement Technology (RET). Some RET concepts have become routine in manufacturing. This volume gathers together seminal RET papers.


Selected Papers on Resolution Enhancement Techniques in Optical Lithography
Language: en
Pages: 910
Authors: F. M. Schellenberg
Categories: Integrated circuits
Type: BOOK - Published: 2004 - Publisher: SPIE-International Society for Optical Engineering

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Optical lithography for integrated circuits is undergoing a renaissance with the adoption of Resolution Enhancement Technology (RET). Some RET concepts have bec
Selected Papers on Resolution Enhancement Techniques in Optical Lithography
Language: en
Pages: 896
Authors: F. M. Schellenberg
Categories:
Type: BOOK - Published: 2004-03-30 - Publisher:

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Optical lithography for integrated circuits is undergoing a renaissance with the adoption of resolution enhancement techniques (RET). Some RET concepts have bec
Resolution Enhancement Techniques in Optical Lithography
Language: en
Pages: 238
Authors: Alfred Kwok-Kit Wong
Categories: Science
Type: BOOK - Published: 2001 - Publisher: SPIE Press

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Ever-smaller IC devices are pushing the optical lithography envelope, increasing the importance of resolution enhancement techniques. This tutorial encompasses
Resolution Enhancement Techniques in Deep UV Optical Lithography for the 90nm Silicon Technological Node and Below
Language: en
Pages:
Optimization of Resolution Enhancement Techniques in Optical Lithography
Language: en
Pages:
Authors:
Categories: Imaging systems
Type: BOOK - Published: 2009 - Publisher:

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As todays' semiconductor fabrication industry tries to keep up with Moore's Law, which predicts the downscaling of integrated circuit size and the doubling of t