Reliable Rf Power Amplifier Design Based On A Partitioning Design Approach

Front cover -- Titelseite -- Impressum -- Acknowledgments -- Contents -- List of Abbreviations and Acronyms -- Abstract -- Zusammenfassung -- Chapter 1 Introduction -- 1.1 Principle of the Partitioning Design Approach -- 1.2 Dissertation Organization -- Chapter 2 Investigation of Planar-Interconnection -- 2.1 Active Chip Device Interconnection -- 2.1.1 Die Attach -- 2.1.2 Wire Bonding Pad-To-Microstrip -- 2.2 Microstrip-to-Microstrip Interconnection -- 2.2.1 Soldering -- 2.2.2 Multi-Wire Bonding -- 2.2.3 Copper Ribbon -- 2.2.4 Silver- Painting -- Chapter 3 Analysis and Modeling of Passive SMD Components -- 3.1 SMD Resistor -- 3.2 SMD Capacitor -- 3.3 SMD Inductor -- Chapter 4 Modeling of AlGaAs/GaAs HEMT Chip Device -- 4.1 AIGaAs/GaGa HEMT Chip -- 4.2 Modeling Approach Overview -- 4.3 Small-Signal Modeling -- 4.3.1 Extrinsic Parameter Extraction -- 4.3.2 Intrinsic Parameter Extraction -- 4.4 Large-Signal Modeling -- 4.4.1 Gate Current and Charge Models -- 4.4.2 Drain Current Model -- 4.4.3 Model Verification -- Chapter 5 Demonstrator Design of a Class-AB Power Amplifier Following -- 5.1 Micro-Packaged Device Characterization -- 5.1.1 Small-Signal Performance -- 5.1.2 Large-Signal Performance -- 5.2 Bias Network Design -- 5.2.1 Drain Bias Network -- 5.2.2 Gate Bias Network -- 5.3 Matching Network Design -- 5.3.1 Matching Impedance Determination -- 5.4 Power Amplifier Performance Evaluation -- 5.4.1 Small-Signal Performance -- 5.4.2 Large-Signal Performance -- Chapter 6 Conclusions and Outlook -- Appendix -- Appendix A THLR In-Fixture Calibration -- Appendix B Precise Determination of Substrate Permittivity -- Appendix C Schematic Circuit of the Designed Power Amplifier Demonstrator -- Appendix D Power Amplifier Design Following the Conventional Design Approach -- References -- Back cover