On Chip Memory Architecture Exploration Of Embedded System On Chip

AbstractToday's feature-rich multimedia products require embedded system solution with complexSystem-on-Chip (SoC) to meet market expectations of high performance at low cost andlower energy consumption. SoCs are complex designs with multiple embedded processors,memory subsystems, and application specific peripherals. The memory architecture ofembedded SoCs strongly influences the area, power and performance of the entire system.Further, the memory subsystem constitutes a major part (typically up to 70%) of thesilicon area for the current day SoC.The on-chip memory organization of embedded processors varies widely from oneSoC to another, depending on the application and market segment for which the SoC isdeployed. There is a wide variety of choices available for the embedded designers, startingfrom simple on-chip SPRAM based architecture to more complex cache-SPRAM basedhybrid architecture. The performance of a memory architecture also depends on howthe data variables of the application are placed in the memory. There are multiple datalayouts for each memory architecture that are efficient from a power and performanceviewpoint. Further, the designer would be interested in multiple optimal design pointsto address various market segments. Hence a memory architecture exploration for anembedded system involves evaluating a large design space in the order of 100,000 ofdesign points and each design points having several tens of thousands of data layouts.Due to its large impact on system performance parameters, the memory architecture isoften hand-crafted by experienced designers exploring a very small subset of this designspace. The vast memory design space prohibits any possibility for a manual analysis.In this work, we propose an automated framework for on-chip memory architectureexploration. Our proposed framework integrates memory architecture exploration anddata layout to search the design space efficiently. While the memory exploration selectsspecific memory architectures, the data layout efficiently maps the given application onto the memory architecture under consideration and thus helps in evaluating the memoryarchitecture. The proposed memory exploration framework works at both logical andphysical memory architecture level. Our work addresses on-chip memory architecture forDSP processors that is organized as multiple memory banks, with each back can be asingle/dual port banks and with non-uniform bank sizes. Further, our work also addressmemory architecture exploration for on-chip memory architectures that is SPRAM andcache based. Our proposed method is based on multi-objective Genetic Algorithm basedand outputs several hundred Pareto-optimal design solutions that are interesting from aarea, power and performance viewpoints within a few hours of running on a standarddesktop configuration.