Hierarchical Modeling for VLSI Circuit Testing

Hierarchical Modeling for VLSI Circuit Testing
Author: Debashis Bhattacharya
Publisher: Springer Science & Business Media
Total Pages: 168
Release: 2012-12-06
Genre: Computers
ISBN: 1461315271


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Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.


Hierarchical Modeling for VLSI Circuit Testing
Language: en
Pages: 168
Authors: Debashis Bhattacharya
Categories: Computers
Type: BOOK - Published: 2012-12-06 - Publisher: Springer Science & Business Media

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Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the alm
Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits
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Categories: Technology & Engineering
Type: BOOK - Published: 2006-04-11 - Publisher: Springer Science & Business Media

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The modern electronic testing has a forty year history. Test professionals hold some fairly large conferences and numerous workshops, have a journal, and there
Neural Models and Algorithms for Digital Testing
Language: en
Pages: 187
Authors: S.T. Chadradhar
Categories: Computers
Type: BOOK - Published: 2012-12-06 - Publisher: Springer Science & Business Media

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References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9 QUADRATIC 0-1 PROGRAMMING 8S 9. 1 Energy Minimization 86 9. 2 Notation and Tenninology .
Hierarchical Modeling and test generation for digital circuits
Language: en
Pages:
Authors:
Categories:
Type: BOOK - Published: 1990 - Publisher:

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Symbolic Analysis for Automated Design of Analog Integrated Circuits
Language: en
Pages: 302
Authors: Georges Gielen
Categories: Technology & Engineering
Type: BOOK - Published: 2012-12-06 - Publisher: Springer Science & Business Media

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It is a great honor to provide a few words of introduction for Dr. Georges Gielen's and Prof. Willy Sansen's book "Symbolic analysis for automated design of ana