Hiding Memory Latency Using Dynamic Scheduling In Shared Memory Multiprocessors
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Hiding Memory Latency Using Dynamic Scheduling in Shared-memory Multiprocessors
Author | : Stanford University. Computer Systems Laboratory |
Publisher | : |
Total Pages | : 14 |
Release | : 1993 |
Genre | : Multiprocessors |
ISBN | : |
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This paper explores the use of dynamically scheduled processors to exploit the overlap allowed by relaxed models for hiding the latency of reads. Our results are based on detailed simulation studies of several parallel applications. The results show that a substantial fraction of the read latency can be hidden using this technique. However, the major improvements in performance are achieved only at large instruction window sizes."
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