Efficient and Scalable Cache Coherence for Many-Core Chip Multiprocessors

Efficient and Scalable Cache Coherence for Many-Core Chip Multiprocessors
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Release: 2009
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La nueva tendencia para aumentar el rendimiento de los futuros computadores son los multiprocesadores en un solo chip (CMPs). Se espera que en un futuro cercano salgan al mercado CMPs con decenas de procesadores. Hoy en dï¿ưa, la mejor manera de mantener la coherencia de cache en estos sistemas es mediante los protocolos basados en directorio. Sin embargo, estos protocolos tienen dos grandes problemas: una gran sobrecarga de memoria y una alta latencia de los fallos de cache. Esta tesis se ha centrado en estos problemas claves para la eficiencia y escalabilidad del CMP. En primer lugar, se ha presentado una organizaciï¿ưn de directorios escalable. En segundo lugar, se han propuesto los protocolos de coherencia directa, que evitan la indirecciï¿ưn al nodo home y, por tanto, reducen el tiempo de ejecuciï¿ưn de las aplicaciones. Por ï¿ưltimo, se ha desarrollado una polï¿ưtica de mapeo para caches compartidas pero fï¿ưsicamente distribuidas, que reduce la latencia de acceso y garantiza una distribuciï¿ưn uniforme de los datos con el fin de reducir su tasa de fallos. Esto se traduce finalmente en un menor tiempo de ejecuciï¿ưn para las aplicaciones. Abstract: Chip multiprocessors (CMPs) constitute the new trend for increasing the performance of future computers. In the near future, chips with tens of cores will become more popular. Nowadays, directory-based protocols constitute the best alternative to keep cache coherence in large-scale systems. Nevertheless, directory-based protocols have two important issues that prevent them from achieving better scalability: the directory memory overhead and the long cache miss latencies. This thesis focuses on these key issues. The first proposal is a scalable distributed directory organization that copes with the memory overhead of directory-based protocols. The second proposal presents the direct coherence protocols, which are aimed at avoiding the indirection problem of traditional directory-based protocols and, therefore, they i.


Efficient and Scalable Cache Coherence for Many-Core Chip Multiprocessors
Language: en
Pages:
Authors:
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Type: BOOK - Published: 2009 - Publisher:

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La nueva tendencia para aumentar el rendimiento de los futuros computadores son los multiprocesadores en un solo chip (CMPs). Se espera que en un futuro cercano
Efficient and Scalable Cache Coherence for Chip Multiprocessors
Language: en
Pages: 196
Authors: Alberto Ros
Categories:
Type: BOOK - Published: 2010-02 - Publisher: LAP Lambert Academic Publishing

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Chip multiprocessors (CMPs) constitute the new trend for increasing the performance of future computers. In the near future, chips with tens of cores will becom
Efficient and Scalable Manycores
Language: en
Pages: 232
Authors: José Luis Abellán
Categories:
Type: BOOK - Published: 2013 - Publisher: LAP Lambert Academic Publishing

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Continuous advances in silicon technology have enabled a new generation of chip multiprocessors, called manycores. Current designs of these systems comprise man
Scalable Shared Memory Multiprocessors
Language: en
Pages: 360
Authors: Michel Dubois
Categories: Computers
Type: BOOK - Published: 1992 - Publisher: Springer Science & Business Media

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Mathematics of Computing -- Parallelism.
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Language: en
Pages: 155
Authors: Rajeev Balasubramonian
Categories: Technology & Engineering
Type: BOOK - Published: 2011-06-06 - Publisher: Morgan & Claypool Publishers

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A key determinant of overall system performance and power dissipation is the cache hierarchy since access to off-chip memory consumes many more cycles and energ