Analysis Of Cache Networking By Noc And Segmented Bus

Large on-chip caches are the next big thing in the field of multiprocessors. Extensive research has gone into modeling memory cells and designing performance enhanced cache banks, but now is the time to shift our focus towards interconnects, which seem to dominate the proceedings with the continuous shrinkage observed in process technology. As we move down into deep sub-micron technology, the interconnect parameters begin to hinder the advancements in cache utilization. It is important to address this issue by coming up with new interconnection architectures for caches which help us improve the performance in terms of latency, power and throughput of the system. Apart from network on chip and the hybrid architectures presented in earlier works, we propose new on-chip communication architectures and perform mathematical analysis for these new architectures to determine the latency and energy. Further, these mathematical expressions help us explore and bring out a comparative study of these architectures.